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1 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary document title 256m: 8m x 32 mobile ddr sdram revision history revision no. date history 0.0 dec. 11, 2007 initial draft emerging memory & logic solutions inc. 4f korea construction financial cooperation b/d, 30 1-1 yeon-dong, jeju-do, korea zip code : 690-717 tel : +82-64-740-1700 fax : +82-64-740-1750 / homepage : www.emlsi.com the attached datasheets provided by emlsi reserve t he right to change the spec ifications and products. emlsi will answer to your questions abo ut device. if you have any ques tions, please contact the emlsi office.
2 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary 256m : 8m x 32bit mobile ddr sdram table 1: ordering information note : 1. emlsi is not designed or manufactured for use in a device or system that is us ed under circumstance in which human life is p otentially at stake. please contact to the memory marketing team in emlsi when considering the use of a product contained herein for any specifi c purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use. part no. max freq. interface package remark EMD56324P-60(ddr332) 166 ? (cl3), 83 ? (cl2) lvcmos wafer biz. EMD56324P-75(ddr266) 133 ? (cl3), 83 ? (cl2) features 1.8v power supply, 1.8v i/o power lvcmos compatible with multiplexed address. double-data-rate architecture; two data transfers per clock cycle bidirectional data strobe(dqs) four banks operation. mrs cycle with address key programs. cas latency (2, & 3). burst length (2, 4, 8, & 16). burst type (sequential & interleave). differential clock inputs(ck and ckb). emrs cycle with address key programs. pasr(partial array self refresh). ds (driver strength) internal auto tcsr (temperature compensated self refresh) deep power-down(dpd) mode. dm for write masking only. auto refresh and self refresh modes. 64 l refresh period (4k cycle). operating temperature range (-25 ? ~ 85 ? ). general description this EMD56324P is 268,435, 456 bits synchronous double data rate dynamic ram. each 67,108,854 bits bank is organized as 4,096 rows by 512columns by 32 bits, fabricated with emlsi?s high performance cmos technology. this device uses a double data ra te architecture to achieve high- speed operation. the double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the i/o balls. range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
3 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 2: pad description symbol type descriptions ck, ckb input clock : ck and ckb are differential clock inputs. all address and control input signals are sampled on the crossing of the positive edge of ck and negativ e edge of ckb. input and output data is referenced to the crossing of ck and ckb(both directions of crossing). internal clock signals are derived from ck/ ckb. cke input clock enable : cke high activates, and cke low deactivates internal clock signals, and device input buffers and output drivers. taking cke lo w provides precharge power-down and self refresh operation(all banks idle), or active power-down(row active in any bank). cke is synchronous for all functions except for self re fresh exit, which is achieved asynchronously. input buffers, excluding ck, ckb and cke, are di sabled during power-down and self refresh mode which are contrived for low standby power consumption. csb input chip select : csb enables (registered low) and di sables (registered high) the command decoder. all commands are masked when csb is registered high. csb provides for external bank selection on systems with multiple banks. csb is considered part of the command code. rasb, casb, web input command inputs: casb, rasb, and web(al ong with csb) define the command being entered. dm0~dm3 input input data mask: dm is an input mask signal for write data. input data is masked when dm is sampled. high along with that input data during a write access. dm is sampled on both edges of dqs. data mask pins incl ude dummy loading internally, to match the dq and dqs loading. ba0, ba1 input bank address inputs: ba0 and ba1 define to which bank an active, read, write or precharge command is being applied. a0 ~ a11 input address inputs: provide the row address for active commands, and the column address and auto precharge bit for read / write commands, to select one location out of the memory array in the respective bank. the address input s also provide the op-code during a mode register set com- mand. dq0~dq31 i/o data bus: input / output dqs0~dqs3 i/o data strobe: output with read data, input with write data. edge-aligned with read data, center-aligned with write data. used to captur e write data. for x32 device, dqs0 corresponds to the data on dq0-dq7, dqs1 corresponds to the data on dq8-dq15, dqs2 corresponds to the data on dq16-dq23, and dqs3 corresponds to the data on dq24-dq31 . vdd supply power supply
4 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary device operation simplified state diagram power on deep power down precharge all banks idle all banks precharged self refresh mrs emrs auto refresh precharge power down active power down row active burst stop write write a precharge preall read a read power applied dpdsx mrs dpds act refa bst read reada writea pre refsx refs ckel ckeh ckel ckeh write read reada reada pre pre pre writea automatic sequence command sequence act = active bst = burst terminate ckel = enter power-down ckeh =exit power-down dpds = enter deep power-down dpdsx = exit deep power-down emrs = ext. mode reg. set mrs = mode register set pre = precharge preall = precharge all banks refa = auto refresh refs = enter self refresh refsx = exit self refresh read = read w/o auto precharge reada = read with auto precharge write = write w/o auto precharge writea = write with auto precharge read write
5 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary functional block diagram address decoder bank control din dqs dout parallel row - address decoder column - dm mask logic i/o gating sense amplifiers logic refresh counter dm to serial din serial to parallel dqs generator dqs a0 - a11 ba0, ba1 cke ck ckb csb rasb casb web standard mode register extended mode register command decode control logic ? ? ? ? ? ? ? 8,192 256 12 ? ? ? dq0~ dq31 dqs0~ dqs3 dm0~ dm3 bank memory array (4,096 x 256 x 64) x 4 x 4 x 4 64 64 8 1 2 2 12 12 32 32 4 4 4 4 4 32 32 4 address register 14 64 64 driver input buf. input buf. input buf. dout driver
6 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary electrical specifications table 3: absolute maximum ratings note : permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. table 4: dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 o c~ 85 o c for extended) note : 1. under all conditions, vddq must be less than or equal to vdd. 2. these parameters should be tested at the pin on actual compo nents and may be checked at either the pin or the pad in simulat ion. table 5: capacitance (v dd = 1.8v, v ddq = 1.8v, t a = 25 ? , f=1 ? ) parameter symbol value unit voltage on any pin relative to v ss v in ,v out -0.5 ~ 2.5 v voltage on v dd and v ddq supply relative to v ss v dd , v ddq -0.5 ~ 2.5 v storage temperature t stg -55 ~ +150 ? power dissipation p d 1.0 w short circuit current i os 50 v parameter symbol min typ max unit note supply voltage v dd 1.7 1.8 1.95 v 1 v ddq 1.7 1.8 1.95 v 1 input logic high voltage v ih 0.8 x v ddq 1.8 v ddq + 0.3 v2 input logic low voltage v il -0.3 0 0.3 v 2 output logic high voltage v oh 0.9 x v ddq --v i oh = -0.1 v output logic low voltage v ol -- 0.1 x v ddq v i ol = 0. 1 v input leakage current i li -2 - 2 u output leakage current i lo -5 - 5 u pin symbol min max unit note input capacitance (add, ba0~1, rasb, casb, web, csb, cke) c in1 1.5 3.0 ? input capacitance(ck, ckb) c in2 1.5 3.5 ? data & dqs input/output capacitance c out 2.0 4.5 ? input capacitance(dm) c in3 2.0 4.5 ?
7 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 6: dc characteristics recommended operating conditions (voltage referenced to vss = 0v, t a = -25 ? to 85 ? ) parameter symbol test condition version unit -60 -75 operating one bank active-precharge current i dd0 t rc = t rcmin ; t ck = t ckmin ; cke is high; csb is high between valid commands; address inputs are switch- ing; data bus inputs are stable 100 80 ma precharge power-down standby current i dd2p all banks idle, cke is low; csb is high, t ck = t ckmin ; address and control inputs are switching; data bus inputs are stable 0.4 ma precharge power-down standby current with clock stop i dd2ps all banks idle, cke is low; csb is high, ck = low, ckb = high; address and control inputs are switching; data bus inputs are stable 0.4 precharge non power- down standby current i dd2n all banks idle, cke is high; csb is high, t ck = t ckmin ; address and control inputs are switching; data bus inputs are stable 25 20 ma precharge non power- down standby current with clock stop i dd2ns all banks idle, cke is high; csb is high, ck = low, ckb = high; address and control inputs are switching; data bus inputs are stable 55 active power-down standby current i dd3p one bank active, cke is low; csb is high, t ck = t ckmin ; address and control inputs are switching; data bus inputs are stable 8 ma active power-down standby current with clock stop i dd3ps one bank active, cke is low; csb is high, ck = low, ckb = high; address and control inputs are switching; data bus inputs are stable 5 active non power-down standby current i dd3n one bank active, cke is high; csb is high, t ck = t ckmin ; address and control inputs are switching; data bus inputs are stable 25 25 ma active non power-down standby current with clock stop i dd3ns one bank active, cke is high; csb is high, ck = low, ckb = high; address and control inputs are switching; data bus inputs are stable 10 10 ma operating burst read current i dd4r one bank active; bl=4; cl=3; t ck = t ckmin ; continuous read bursts; iout = 0 ma; address inputs are switching; 50% data change each burst transfer 160 130 ma operating burst write current i dd4w one bank active; t ck = t ckmin ; continuous write bursts; address inputs are switching; 50% data change each burst transfer 130 105 ma auto-refresh current i dd5 t rc = t rfcmin ; burst refresh; cke is high; address and control inputs are switching; data bus inputs are stable 120 120 ma self refresh current i dd6 cke is low, ck = low, ckb = high; extended mode reg- ister set to all 0s; address and control inputs are stable; data bus inputs are stable tcsr range 45* 1 85 c full array 250 400 a 1/2 of full array 200 300 1/4 of full array 150 250 deep power-down current i dd8 address and control inputs are stable; data bus inputs are stable 10 10 a
8 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary note : 1. idd specifications are tested af ter the device is properly initialized 2. input slew rate is 1v/ns. 3. definitions for idd: low is defined as v in ? 0.1 * vddq ; high is defined as v in ? 0.9 * vddq ; stable is defined as inputs stable at a high or low level ; switching is defined as : - address and command : inputs changing between high and low once per two clock cycles ; - data bus inputs : dq ch anging betw een high and low once per clo ck cycle ; dm and dqs are stable table 7: ac operat ing test conditions (v dd = 1.7v ~ 1.95v, t a = -25 ? ~85 ? for extended) note : 1. under all conditions, vddq must be less than or equal to vdd. 2. these parameters should be tested at the pin on actual compo nents and may be checked at either the pin or the pad in simulat ion. 3. ck and ckb crossing voltage. parameter value unit note ac input levels(vih/vil) 0.8 ? v ddq / 0.2 ? v ddq v input timing measurement reference level 0.5 ? v ddq v input rise and fall time 1.0 v / j output timing measurement reference level 0.5 ? v ddq v vix 0.4 ? v ddq (min) / 0.6 ? v ddq (max) v3 output load condition see figure 2 1.8v 13.9 ? v oh (dc) = 0.9 ? v ddq , i oh = -0.1 v v ol (dc) = 0.1 ? v ddq , i ol = 0.1 v 20 ? z0=50 ? vtt=0.5 ? v ddq 50 ? 20 ? figure 1. dc output load circuit figure 2. ac output load circuit output output 10.6 ?
9 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 8: operating ac parameter (ac operating conditions unless otherwise noted) parameter sym- bol -60 -75 unit note min max min max dq output access time from ck/ckb t ac 2 5 2.5 6.0 ns 3 dqs output access time from ck/ckb t dqsck 2 5 2.5 6.0 ns clock high-level width t ch 0.45 0.55 0.45 0.55 t ck clock low-level width t cl 0.45 0.55 0.45 0.55 t ck clock half period t hp min (t cl ,t ch ) min (t cl ,t ch ) ns clock cycle time cl = 3 t ck 6 100 7.5 100 ns cl = 2 12 100 12 100 ns dq and dm input setup time t ds 0.6 0.75 ns 4,5 dq and dm input hold time t dh 0.6 0.75 ns 4,5 dq and dm input pulse width t dipw 1.8 2.5 ns address and control input setup time t is 1.1 1.3 ns 1 address and control input hold time t ih 1.1 1.3 ns 1 address and control input pulse width t ipw 2.6 2.6 ns dq & dqs low-impedance time from ck/ckb t lz 1.0 1.0 ns dq & dqs high-impedance time from ck/ckb t hz 56.0 ns dqs - dq skew t dqsq 0.5 0.6 ns dq / dqs output hold time from dqs t qh t hp -t qhs t hp -t qhs ns data hold skew factor t qhs 0.65 0.75 ns write command to 1st dqs latching transition t dqss 0.75 1.25 0.75 1.25 t ck dqs input high-level width t dqsh 0.4 0.6 0.4 0.6 t ck dqs input low-level width t dqsl 0.4 0.6 0.4 0.6 t ck dqs falling edge to ck rising - setup time t dss 0.2 0.2 t ck dqs falling edge from ck rising - hold time t dsh 0.2 0.2 t ck mode register set command period t mrd 22 t ck write preamble setup time t wpres 00ns write postamble t wpst 0.4 0.6 0.4 0.6 t ck write preamble t wpre 0.25 0.25 t ck
10 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary note: table 9: input setup/hold slew rate 1. this derating table is used to increase t is /t ih in the case where the input slew rate is below 1.0v/ns. 2. minimum 5ck of t dal (= t wr + t rp ) is required because it need minimum 2ck for t wr and minimum 3ck for t rp . 3. t ac (min) value is measured at the high vdd(1.95v) and cold temperature(-25c). t ac (max) value is measured at the low vdd(1.7v) and hot temperature(85c). t ac is measured in the device with half driver strength a nd under the ac output load condition (fig.2 in page 8). parameter sym- bol -60 -75 unit note min max min max read preamble cl = 2 t rpre 0.5 1.1 0.5 1.1 t ck cl = 3 0.9 1.1 0.9 1.1 t ck read postamble t rpst 0.4 0.6 0.4 0.6 t ck active to precharge command period t ras 42 70,000 45 70,000 ns active to active command period t rc 60 60 ns auto refresh to active / auto refresh command period t rfc 80 80 ns 6 active to read or write delay t rcd 18 18 ns precharge command period t rp 18 22.5 ns active bank a to active bank b delay t rrd 12 15 ns column address to column address delay t ccd 11 t ck write recovery time t wr 22 t ck auto precharge write recovery + precharge time t dal t wr+ t rp t wr+ t rp 2 internal write to read command delay t wtr 11 t ck self refresh exit to next valid command delay t xsr 120 120 ns exit power down to next valid command delay t xp t ck +t is t ck +t is cke min. pulse width(high and low pulse width) t cke 12 t ck refresh period t ref 64 64 ms input setup/hold slew rate ? t is ? t ih (v/ns) (ps) (ps) 1.0 0 0 0.8 +50 +50 0.6 +100 +100
11 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 10: i/o setup/hold slew rate 4. this derating table is used to increase t ds /t dh in the case where the i/o slew rate is below 1.0v/ns. table 11: i/o delta rise/fall rate(1/slewrate) 5. this derating table is used to increase t ds /t dh in the case where the dq and dqs slew rates differ. the delta rise/fall rate is calculated as 1/slewrate1-1/slewrate2. for example, if slew rate 1 = 1.0v/ns and slew rate 2 = 0.8v/ns, then the delta rise/fall rate = - 0.25ns/v. 6. maximum burst refresh cycle : 8 i/o setup/hold slew rate ? t ds ? t dh (v/ns) (ps) (ps) 1.0 0 0 0.8 +75 +75 0.6 +150 +150 delta rise/fall rate ? t ds ? t dh (ns/v) (ps) (ps) 000 ? 0.25 +50 +50 ? 0.5 +100 +100
12 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary functional description the 256mb mobile ddr sdram is a high-speed cmos, dynamic random-access memory containing 268,435,456- bits. it is internally configured as a quad-bank dram. each of the 67,108,864-bit banks is organized as 4,096 rows by 512 columns by 32 bits. the 256mb mobile ddr sdram uses a double data rate ar chitecture to achieve high-speed operation. the double data rate architecture is essentially a 2n-prefetch archit ecture, with an interface designed to transfer two data words per clock cycle at the i/o ball s. single read or write access for the 256mb mobile ddr sdram consists of a single 2n- bit wide, one-clock-cycle data transfer at the internal dram core and two co rresponding n-bit wid e, one-half-clock- cycle data transfers at the i/o balls. read and write accesses to the mobile ddr sdram are burst oriented; accesses start at a selected location and con- tinue for a programmed number of locations in a programm ed sequence. accesses begin with the registration of an active command, which is then followed by a read or write command. the address bits registered coincident with the active command are used to se lect the bank and row to be accessed (ba0, ba1 select the bank; a0-a11 select the row). the address bits registered coincident with the read or write command are used to select the start- ing column location for the burst access. it should be noted that the dll signal that is typically used on standard ddr devices is not necessary on the mobile ddr sdram. it has been omitted to save power. prior to no rmal operation, the mobile ddr sdram must be initial- ized. the following sections provide detailed information co vering device initialization, register definition, command descriptions and device operation. initialization mobile ddr sdrams must be powered up and initialized in a predefined manner. operational procedures other than those specified may result in undefined op eration. if there is an interruption to the device power, the initialization rou- tine should be followed to ensure proper functionality of th e mobile ddr sdram. the cloc k stop feature is not avail- able until the device has been properly initialized. to properly initialize the mobile ddr sdram, this sequence must be followed: 1. to prevent device latch-up, it is recommended the co re power (vdd) and i/o power (vddq) be from the same power source and brought up simultaneously. if separate power sources ar e used, vdd must lead vddq. 2. once power supply voltages are stable and the cke has been driven high, it is safe to apply the clock. 3. once the clock is stable, a 200 s (minimum) delay is required by the mobile ddr sdram prior to applying an exe cutable command. during this time, nop or de select commands must be issued on the command bus. 4. issue a precharge all command. 5. issue nop or deselect comm ands for at least trp time. 6. issue an auto refresh command fo llowed by nop or deselect commands for at least trfc time. issue a second auto refresh command followed by nop or deselect commands for at least trfc time. as part of the initialization sequence, two auto refresh co mmands must be issued. typically, both of these com mands are issued at this stage as described abov e. alternately, the second auto-refresh command and nop or deselect sequence can be issued between steps 10 and 11. 7. using the load mode register command, load the standard mode register as desired. 8. issue nop or deselect comm ands for at least tmrd time. 9. using the load mode register command, load the extended mode register to the desired operating modes. note that the sequence in which the standard and extended mode registers are programmed is not critical. 10. issue nop or deselect comma nds for at least tmrd time. 11. the mobile ddr sdram has been properly initialized and is ready to receive any valid command.
13 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary register definition mode registers the mode registers are used to define t he specific mode of operation of the mobile ddr sdram. there are two mode registers used to specify the operational characteristics of th e device. the standard mode register, which exists for all sdram devices, and the extende d mode register, which exists on all mobile sdram devices. standard mode register the standard mode register definition incl udes the selection of a burst length, a burst type, a cas latency and an oper- ating mode, as shown in page 15. the standard mode re gister is programmed via the load mode register set command (with ba0 = 0 and ba1 = 0) and will retain the stor ed information until it is programmed again. reprogram- ming the standard mode register will not alter the contents of the memory, provided it is performed correctly. the mode register must be loaded (reloaded) when all banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating the subsequent operat ion. violating either of th ese requirements will result in unspecified operation. mode register bits a0-a2 specify the burst length, a3 s pecifies the type of burst (sequential or interleaved), a4-a6 specify the cas latenc y, and a7-a11 specify the operating mode. note: standard refers to meeting jede c-standard mode register definitions. burst length read and write accesses to the mobile ddr sdram are burst oriented, with the burst length being programmable, as shown in page 15. the burst length determines the maximum number of column locations that can be accessed for a given read or write command. burst lengths of 2, 4, 8, or 16 are available for both the sequential and the inter- leaved burst types. reserved states should not be used, as unknown operatio n or incompatibility with future versions may result. burst type accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected by a3. the ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address. see table 17~20 on page 17~18 for more information. cas latency the cas latency is the delay, in clock cycles, between the registration of a read command and the availability of the first bit of output da ta. the latency can be set to 2 or 3 clocks, as shown in page 15. for cl = 3, if the read command is registered at clock ed ge n, then the data will nominally be available at (n + 2 clocks + tac). for cl = 2, if the read command is registered at clock edge n, th en the data will be nominally be avail- able at (n + 1 clock + tac). reserved states should not be used as unknown operation or incompatibility with future versions may result. operating mode the normal operating mode is selected by issuing a load mode register set command with bits a7-a11 each set to zero, and bits a0-a6 set to the desired values. all other combinations of values for a7-a11 are reserved for future use and/or test modes. test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result.
14 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary extended mode register the extended mode register controls fu nctions specific to low power operatio n. these additional functions include drive strength, temperature co mpensated self refresh, and partial array self refresh. this device has default values for the extended mode re gister (if not programmed, the device will operate with the default values . pasr = full array, ds = full drive). temperature compensated self refresh on this version of the mobile ddr sdram, a temperature sensor is implemented for automatic control of the self refresh oscillator on the device. programming of the tem perature compensated self refresh (tcsr) bits will have no effect on the device. the self refresh oscillator will cont inue refresh at the factory programmed optimal rate for the device temperature. partial array self refresh for further power savings during self refresh, the pasr feature allows the controller to select the amount of memory that will be refreshed during self refresh. low power ddr sdram supports 3 kinds of pasr in self refresh mode : full array, 1/2 of full array and 1/4 of full array. output driver strength because the mobile ddr sdram is designed for use in smaller systems that are mostly point to point, an option to control the drive strength of the output buffers is available. drive stre ngth should be selected based on the expected loading of the memory bus. bits a5 and a6 of the extended mode register can be used to select the driver strength of the dq outputs. stopping the external clock one method of controlling the power efficiency in applications is to throttle the clock which controls the mobile ddr sdram. there are two basic ways to control the clock: 1. change the clock frequency, when the data tran sfers require a different rate of speed. 2. stopping the clock altogether. both of these are specific to the appl ication and its requirements and both allow power savings due to possible less transitions on the clock path. the mobile ddr sdram allows the clock to change frequency during operation, only if all the timing parameters are met with respect to that change and all refresh requirements are satisfied. the clock can also be stopped all together, if there are no data accesses in progress, either writes or reads that would be effected by this change; i.e., if a write or a r ead is in progress the entire data burst must be through the pipeline prior to stopping the clock. cke must be held high with ck = low and ckb = high for the full duration of the clock stop mode. one clock cycle and at least one nop is required after the clock is restarted before a valid com- mand can be issued. it is recommended that the mobile ddr sdram should be in a precharged state if any changes to the clock frequency are expected. this will eliminate timing violations that may otherwise occu r during normal operational accesses. ba1=0 ba0=0 ba0=1 ba1=0 ba1=0 ba1=0 ba0=0 ba1=1 ba1=1 ba0=0 ba0=1 - full array - 1/2 array - 1/4 array ba1=1 ba1=1 ba1=0 ba1=0 ba0=0 ba0=1 ba1=1 ba0=1 ba0=0 ba0=0 ba0=1 ba1=1 ba0=1 partial self refresh area
15 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 12: mode register field table to program modes register programmed with normal mrs note : 1. rfu(reserved for future use) should stay ?0? during mrs cycle. table 13: normal mrs mode note : 1. mrs can be issued only at all bank precharge state. 2. minimum trp is required to issue mrs command. address ba0 ~ ba1 a11 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu *1 operating mode cas latency bt burst length operating mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 ddr 00 mode register set 000 reserved 0 sequential 000 reserved 01 reserved 001 reserved 1 interleave 001 2 10 reserved 010 2 mode select 0 1 0 4 11 reserved 011 3 ba1 ba0 mode 0 1 1 8 -- - 100 reserved 00 setting for nor- mal mrs 100 16 -- - 101 reserved 101 reserved -- - 110 reserved 110 reserved -- - 111 reserved 111 reserved mode register set any command *1 t ck ckb ck t rp 2 clock min. command precharge all banks 01 2 34 5 6 7 8 *2 mode register set
16 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 14: register programmed with extended mrs note : 1. rfu(reserved for future use) should stay ?0? during mrs and emrs cycle. table 15: emrs for pasr(p artial array self refr esh) & ds(driver strength) table 16: internal temperature compensated self refresh (tcsr) note : 1. in order to save power consumption, mobile ddr sdram includes the internal temperature sensor and control units to control t he self refresh cycle automatically according to the two temperature range : max 85 ? , max 45 ? 2. if the emrs for external tcsr is issued by the controller, this emrs code for tcsr is ignored. 3. it has +/- 5 ? tolerance. address ba1 ba0 a11 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function mode select rfu *1 ds rfu *1 pasr mode select driver strength pasr ba1 ba0 mode a6 a5 driver strength a2 a1 a0 size of refreshed array 00 normal mrs 00 full 000 full array 01 reserved 01 1/2 001 1/2 of full array 10 emrs for ddr sdram 10 1/4 010 1/4 of full array 11 reserved 11 reserved 011 reserved 100 reserved 101 reserved 110 reserved 111 reserved temperature range self refresh current (i dd 6) unit full array 1/2 of full array 1/4 of full array max 85 ? 400 300 250 u max 45 ? 250 200 150
17 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary burst sequence table 17: burst length = 2 table 18: burst length = 4 table 19: burst length = 8 initial address sequential interleave a0 00101 11010 initial address sequential interleave a1 a0 0001230123 0112301032 1023012301 1130123210 initial address sequential interleave a2 a1 a0 0000123456701234567 0011234567010325476 0102345670123016745 0113456701232107654 1004567012345670123 1015670123454761032 1106701234567452301 1117012345676543210
18 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 20: burst length = 16 initial address sequential interleave a3 a2 a1 a0 0 0 0 0 01234567891011121314150123456789101112131415 0 0 0 1 12345678910111213141501032547698111013121514 0 0 1 0 23456789101112131415012301674510118914151213 0 0 1 1 34567891011121314150123210765411109815141312 0 1 0 0 45678910111213141501234567012312131415891011 0 1 0 1 56789101112131415012345476103213121514981110 0 1 1 0 67891011121314150123456745230114151213101189 0 1 1 1 78910111213141501234567654321015141312111098 1 0 0 0 89101112131415012345678910111213141501234567 1 0 0 1 91011121314150123456789811101312151410325476 1 0 1 010111213141501234567891011891415121323016745 1 0 1 111121314150123456789101110981514131232107654 1 1 0 012131415012345678910111213141589101145670123 1 1 0 113141501234567891011121312151498111054761032 1 1 1 014150123456789101112131415121310118967452301 1 1 1 115012345678910111213141514131211109876543210
19 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary commands deselect the deselect function (csb high) prevents new commands from being ex ecuted by the mobile ddr sdram. the mobile ddr sdram is effectivel y deselected. operations already in progress are not affected. no operation (nop) the no operation (nop) command is used to instruct the selected ddr sdram to perform a nop (csb = low, rasb = casb = web = high). this prevents unwanted commands from being registered durin g idle or wait states. operations already in progress are not affected. load mode register the mode register is loaded via inputs a0-a11, ba0 , ba1. the load mode register and load extended mode register commands can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. the values of the mode register and extended mode re gister will be retained even when exiting deep power-down. active the active command is used to open (or activate) a row in a particular bank for a subsequent access. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a11 selects the row. this row remains active (or open) for accesses until a precharge command is issued to that bank. a precharge command must be issued before opening a different row in the same bank. read the read command is used to initiate a burst read access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is select ed, the row being accessed will be pre- charged at the end of the read burst ; if auto precharge is not selected, the row will remain open for subsequent accesses. write the write command is used to initiate a burst write access to an active row. the value on the ba0, ba1 inputs selects the bank, and the address provided on inputs a0-a8 selects the starting column location. the value on input a10 determines whether or not auto precharge is used. if auto precharge is selected, the row being accessed will be precharged at the end of the write burst ; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dqs is written to t he memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresponding data inputs will be ignored, and a write will not be executed to that byte/column location. precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a spec ified time (trp) after the precharge command is issued. except in the case of concurrent au to precharge, where a read or write command to a different bank is allowed as long as it does not interrupt the data transfer in the cu rrent bank and does not violate any other timing parameters. input a10 determines whether one or all ba nks are to be precharged, and in the ca se where only one bank is to be pre- charged, inputs ba0, ba1 select the bank. otherwise ba0, ba1 are treated as ?don?t care?. once a bank has been precharged, it is in the idle state and must be activat ed prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if there is no open row in that bank (idle stat e), or if the pre- viously open row is already in the process of precharging.
20 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary auto precharge auto precharge is a feature which performs the same individual-bank precharge function described above, but without requiring an explicit command. this is accomplished by using a10 to enable auto precharge in conjunction with a specific read or write command. a precharge of the bank/row that is addressed with the read or write com- mand is automatically performed upon completion of the r ead or write burst. auto precharge is nonpersistent in that it is either enabled or disabled for each individ ual read or write command. this device supports concurrent auto precharge if the command to the other bank does not interrupt the data transfer to the current bank. auto precharge ensures that the precharge is initiated at the earliest valid stage within a burst. this ?earliest valid stage? is determined as if an explicit precharge command was issued at the ear liest possible time, without violating tras (min), as described for each burst type in ?operations?. the user must not issue another command to the same bank until the precharge time (trp) is completed. burst terminate the burst terminate command is used to truncate r ead bursts (with auto precharge disabled). the most recently registered read command prior to the burst terminate command will be truncated, as shown in ?oper- ations?. the open page which the read bur st was terminated from remains open. auto refresh auto refresh is used during normal operation of t he mobile ddr sdram and is analogous to cas-before- ras (cbr) refresh in fpm/edo drams. this command is nonpe rsistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controlle r. this makes the address bits a ?don?t care? during an auto refresh command. the 256mb mobile ddr sdram requires auto refresh cycles at an average inter- val of 15.625 s (maximum). to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. although not a jedec requirement, to provide for future functionality features, cke must be active (high) during the auto refresh period. the auto re fresh period begins when the auto refresh command is registered and ends trfc later. pre ckb ck command cke = high auto refresh cmd t rp t rfc auto refresh
21 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary self refresh the self refresh command can be used to retain data in the mobile ddr sdram, even if the rest of the system is powered down. when in the self refresh mode, the mo bile ddr sdram retains data without external clocking. the self refresh command is initiated like an auto refresh command except cke is disabled (low). all com- mand and address input signals except cke are ?don?t care? during self refresh. during self refresh, the device is refreshed as identified in the external mode register (see pasr setting). for the full array refresh, all four banks are refreshed simult aneously with the refresh frequency set by an internal self refresh oscillator. this oscillator changes due to the temper ature sensor?s input. as the ca se temperature of the mobile ddr sdram increases, the oscillation frequency will cha nge to accommodate the change of temperatur e. this hap- pens because the dram capacitors lose charge faster at higher temperatures. to ensure efficient power dissipation during self refresh, the oscillator will change to refresh at the slowest rate possible to maintain the devices data. the procedure for exiting self refresh requires a sequence of commands. first, ck must be stable prior to cke going back high. once cke is high, the mobile ddr sdram must have nop commands issued for txsr is required for the completion of any internal refresh in progress. deep power-down the operating mode deep power-down achieves maximum powe r reduction by eliminating the power of the whole memory array of the device. array data will not be retained once the de vice enters deep power-down mode. this mode is entered by having all banks idle then csb and web held low with rasb and casb held high at the rising edge of the clock, while cke is low. this mode is exited by asserting cke high. self ckb ck command cke = high cmd t xsr active refresh self refresh t is
22 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary operations bank/row activation the bank activation command is is sued by holding c asb and web high with csb and rasb low at the rising edge of the clock(ck). the ddr sdram has four independent banks, so two bank select addresses(ba0, ba1) are required. the bank activation command must be applied before any r ead or write operation is executed. the delay from the bank activation command to the first read or write comm and must meet or exceed the minimum of ras to cas delay time(trcd min). once a bank has been activated, it must be precharged before another bank activation com- mand can be applied to the same bank. the minimum time interval between interleaved bank activation com- mands(bank a to bank b and vice versa) is the bank to bank delay time(trrd min). bank activation command cycle ckb ck address command 0 1 2 tn tn+1 tn+2 bank b row addr. bank a row. addr. 3 bank a row address bank a col. addr. bank a activate nop nop write with auto precharge bank b activate nop bank a activate row cycle time(trc) : don't care ras - cas delay(t rcd ) ras - ras delay time(t rrd )
23 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary reads read bursts are initiated with a read command. the starting column and bank addresses are provided with the read command and auto precharge is either enabled or disabled for that burst access. if auto precharge is enab led, the row being accessed is precharged at the completion of the burst. for the read commands used in the fo llowing illustrations, auto precharge is disabled. during read bursts, the valid data-out element from the st arting column address will be available following the cas latency after the read command. each subsequent data-out element will be va lid nominally at the next positive or negative clock edge (i.e., at the next crossing of ck and ckb). dqs is driven by t he mobile ddr sdram along with output data. the initial low state on dqs is known as the read preamble; the low state coincident with the last data- out element is known as the read postamble. upon completion of a burst, assuming no other comm ands have been initiated, the dqs will go high-z. data from any read burst may be concatenated with or truncated with data from a subsequent read command. in either case, a continuous flow of data can be maintained. t he first data element from the new burst follows either the last element of a completed burst or the last desired data element of a longer burst wh ich is being truncated. the new read command should be issued x cycles after the first read command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). a read command can be initiated on any clock cycle following a previous read command. ckb ck 0 1 34 567 8 2 command dqs dq?s dqs dq?s read nop nop nop nop nop nop nop nop dout 0 dout 1 dout 2 dout 3 dout 0 dout 1 dout 2 dout 3 t rpre t rpst cl2 cl3 burst read operation < burst length=4, cas latency=2, 3) > t rpre
24 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary truncated reads data from any read burst may be truncated with a b urst terminate command. the burst terminate latency is equal to the read (cas) latency, i.e., the burst te rminate command should be issued x cycles after the read command, where x equals the number of des ired data element pairs (pairs are required by the 2n-prefetch architec- ture). data from any read burst must be completed or trunca ted before a subsequent write command can be issued. if truncation is necessary, the burst terminate command must be used. a read burst may be followed by, or truncated with, a precharge command to the same bank provided that auto precharge was not activated. the precharge command should be issued x cycles after the read command, where x equals the number of desired data element pairs (pai rs are required by the 2n-pref etch architecture). follow- ing the precharge command, a subsequ ent command to the same bank ca nnot be issued until trp is met. note: part of the row precharge time is hidd en during the access of the last data elements. read interrupted by a read < burst length=4, cas latency = 2 > ckb ck 0 1 34 567 8 2 command dqs dq?s read a read b nop nop nop nop nop nop nop dout a0 cl2 dout a1 dout b0 dout b1 dout b2 dout b3 read interrupted by a write & burst stop < burst length=4, cas latency = 2 > ckb ck 0 1 34 567 8 2 command dqs dq?s read burst stop nop write nop nop nop nop nop dout 0 cl2 dout 1 din 0 din 1 din 2 din 3 read interrupted by a precharge < burst length=8, cas latency = 2 > ckb ck 0 1 34 567 8 2 command dqs dq?s read precharge nop nop nop nop nop nop nop dout 0 cl2 dout 1 dout 4 dout 5 dout 6 dout 7 dout 2 dout 3 interrupted by precharge 1t ck
25 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary writes write bursts are initiated with a write command. the st arting column and bank addresses are provided with the write command, and auto precharge is either enabled or disabled for that access. if auto precharge is enabled, the row being accessed is precharged at the completion of the burst. for the write commands used in the following illus- trations, auto precharge is disabled. during write bursts, th e first valid data-in element will be registered on the first rising edge of dqs following the write command, and s ubsequent data elements will be registered on successive edges of dqs. the low state on dqs bet ween the write command and the first rising edge is known as the write preamble; the low state on dqs following the last data-in element is known as the write postamble. the time between the write command and the first correspondi ng rising edge of dqs (tdq ss) is specified with a rel- atively wide range (from 75 percent to 125 percent of one clock cycle). upon completion of a burst, assuming no other commands have been initiated, the dqs will remain high-z and any additional input data will be ignored. data for any write burst may be concatenated with or trunc ated with a subsequent write command. in either case, a continuous flow of input data can be maintained. the new write command can be issued on any positive edge of clock following the previous write command. the first data el ement from the new burst is applied after either the last element of a completed burst or the last desired data el ement of a longer burst whic h is being truncated. the new write command should be issued x cycles after the first write command, where x equals the number of desired data element pairs (pairs are required by the 2n-prefetch architecture). burst write operation < burst length=4 > ckb ck 0 1 3 2 command dqs dq?s nop write a nop nop nop nop nop nop write b dqs dq?s don?t care t wpres t wpre t dqsl t dqsh t dsh t dsh t wpst t wpres t wpre t dqss t dqss t dqsh t dss t dss t wpst t dqsl case 1: t dqss = min case 2: t dqss = max
26 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary write interrupted by a write < burst length=4 > ckb ck 0 1 34 567 8 2 command dqs dq?s nop write a nop write b nop nop nop nop nop din a0 din a1 din b0 din b1 din b2 din b3 1t ck write interrupted by a read & dm < burst length=8, cas latency =2 > ckb ck 0 1 34 567 8 2 command dqs dq?s nop write nop nop nop read nop nop nop din 0 din 1 din 2 din 3 din 4 din 5 dqs dq?s din 0 din 1 din 2 din 3 din 4 din 5 dm dm din 6 din 7 dout 0 dout 1 dout 2 dout 3 t wtr t wtr t dqssmax t wpres t dqssmin t wpre din 6 din 7 dout 1 dout 0 dout 2 dout 3 cl2 cl2 t wpres t wpre
27 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary nop write a nop nop nop nop precharge a write b nop write interrupted by a precharge & dm < burst length = 8 > 0 1 2 3 4 5 6 7 8 din a0 din a1 din a2 din a3 din b0 din a0 din a1 din a2 din a3 din b0 din b1 t dqssmax t dqssmin ckb ck command dqs dq?s dm dqs dq?s dm t wr din a4 din a5 din a6 din a7 din a4 din a5 din a6 din a7 t dqssmax din b t dqssmin din b read burst stop nop nop nop nop nop nop nop burst stop < burst length = 4, cas latency = 2, 3 > 0 1 2 3 4 5 6 7 8 dout0 dout1 dout0 dout1 cl = 3 ckb ck command dqs dq?s dqs dq?s the burst ends after a delay equal to the cas latency. cl = 2
28 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary precharge the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access some specified time (trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in the case where only one bank is to be precharged, inputs ba0, ba1 select the bank. when a ll banks are to be precharged, inputs ba0, ba1 are treated as don?t care. once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. write nop nop nop nop nop nop nop nop dm masking < burst length = 8 > 0 1 2 3 4 5 6 7 8 t dqss ckb ck command dqs dq?s dm din 4 din 5 din 6 din 7 din 0 din 1 din 2 din 3 t ds t dh masked by dm = h bank a nop nop nop nop nop nop nop read with auto precharge < burst length = 4, cas latency = 2, 3 > 0 1 2 3 4 5 6 7 8 cl = 2 ckb ck command dqs dq?s dout0 dout1 dout2 dout3 active read auto precharge 9 nop dqs dq?s dout0 dout1 dout2 dout3 cl = 3 t ras(min.) t rp begin auto-precharge
29 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary power-down power-down is entered when cke is registered low. if power-down occurs when all banks are idle, this mode is referred to as precharge power-down; if power-down occurs when there is a row active in any bank, this mode is referred to as active power-down. entering power-down d eactivates the input and output buffers, including ck and ckb. exiting power-down requires the device to be at the same voltage as when it entered power-down and a stable clock. note: the power-down duration is limited by the refresh requirements of the device. while in power-down, cke low must be maintained at the inputs of the mobile ddr sdram, while all other input sig- nals are don?t care. the power-down state is synchronously ex ited when cke is register ed high (in conjunction with a nop or deselect command). nops or deselect comman ds must be maintained on the command bus until t xp is satisfied. bank a nop nop nop nop nop nop nop write with auto precharge < burst length = 4 > 0 1 2 3 4 5 6 7 8 ckb ck command dqs dq?s din 0 din 1 din 2 din 3 active write auto precharge 9 nop t wr bank can be reactivated at completion of t rp 10 nop t rp t dal internal precharge start 11 nop ckb ck command cke = high t is active precharge precharge power down entry active power down entry read active power down exit t xp power down
30 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary table 21: simplified truth table (v=valid, x =don't care, h=logic high, l=logic low) note : 1. op code : operand code a0 ~ a11 & ba0 ~ ba1 : program keys. (@emrs/mrs) 2. emrs/mrs can be issued only at all banks precharge state. a new command can be issued 2 clk cycles after emrs or mrs. 3. auto refresh functions are the same as cbr refresh of dram. auto/self refresh can be issued only at all banks precharge state. 4. ba0 ~ba1 : bank select addresses. 5. if a10/ap is ?high? at row precharge, ba0 and ba1 are ignored and all banks are selected. 6. during burst write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at t rp after the end of burst. 7. burst stop command is valid at every burst length. 8. dm sampled at the rising and falling edges of the dqs and data-in are masked at the both edges(write dm latency is 0). 9. this combination is not defined for any functi on, which means ?no operation(nop)? in ddr sdram. 10. the deep power down mode is exited by asserting cke high and full initialization is required after exiting deep power down mode. command cken-1 cken csb rasb casb web ba0,1 a10/ap a11 a9 ~ a0 note register mode register set h x l l l l op code 1, 2 refresh auto refresh h h ll lh x 3 self refresh entry l 3 exit l h lh hh x 3 hx x x 3 bank active & row addr. h x l l h h v row address read & column address auto precharge disable hxlhlhv l column address (a0~a8) 4 auto precharge enable h4 write & column address auto precharge disable hxlhllv l column address (a0~a8) 4 auto precharge enable h4, 6 burst stop h x l h h l x 7 precharge bank selection hxllhl vl x all banks xh 5 active power down entry h l hx x x x lh hh exit l h hx x x lh hh precharge power down entry h l hx x x x lh hh exit l h hx x x lh hh deep power down entry h l l h h l x exit l h h x x x 10 dm h x x 8 no operation command(nop) h x hx x x x 9 lh hh 9
31 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary timing diagrams basic timing (setup, hold a nd access time @ bl=4, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high active read write bab baa baa ra ca cb qa0 qa1 qa2 qa3 db0 db1 db2 db3 t ch t cl t ck t is t ih t ds t dh t ds t dh t dqss t dsc t dqsh t dqsl t rpst t wpre t rpre hi-z hi-z dqs dq q0 q1 q2 q3 t rpre t dqsq t qhs t rpst dqs dq d0 d1 d2 d3 t wpre t wpst t ds t dh t dsc read operation write operation disable auto precharge disable auto precharge ra : don?t care
32 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary multi bank interleaving read (@ bl=4, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high active read qa0 qa1 qa2 qa3 qb0 qb1 qb2 qb3 t ch t cl t ck active read baa ra bab baa bab rb ca cb disable auto precharge disable auto precharge ra rb
33 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary multi bank interleaving write (@ bl=4) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high active write da0 da1 da2 da3 db0 db1 db2 db3 t ch t cl t ck active write baa ra bab baa bab rb ca cb t rcd disable auto precharge disable auto precharge ra rb
34 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary read with auto precha rge (@ bl=8, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high read qa0 qa1 qa2 qa3 qa4 qa5 qa6 qa7 t ch t cl t ck active baa ca baa ra t rp auto precharge start(note 1) note 1 the row active command of the precharged bank can be issued after trp from this point the new read/write command of another activated bank c an be issued from this point at burst read/write with auto precharge, cas interrupt of the same is illegal enable auto precharge ra
35 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary write with auto precharge (@ bl=8) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high write t ch t cl t ck active baa ca baa ra auto precharge start(note 1) da0 da1 da2 da3 da4 da5 da6 da7 t rp t wr t dal note 1 the row active command of the precharged bank can be issued after trp from this point the new read/write command of anot her activated bank can be issued from this point at burst read/write with auto precharge, cas interrupt of the same bank/another bank is illegal enable auto precharge ra
36 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary write followed by precharge (@ bl=4) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high write t ch t cl t ck pre baa ca baa da0 da1 da2 da3 t wr charge single bank disable auto precharge
37 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary write interrupted by precharge & dm (@ bl=8) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high write t ch t cl t ck ca cc da0 da1 da2 da3 da4 da5 da6 da7 cb baa bac bab baa pre charge write write t ccd db0 db1 dc0 dc1 dc2 dc3 dc4 dc5 disable auto precharge single bank disable auto precharge
38 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary write interrupted by a read (@ bl=8, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high read qb0 qb1 qb2 qb3 qb4 qb5 qb6 qb7 t ch t cl t ck write ca cb baa bab t wtr da0 da1 da2 da3 da4 da5 disable auto precharge disable auto precharge
39 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary read interrupted by prec harge (@ bl=8, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high read qa0 qa1 qa2 qa3 qa4 qa5 t ch t cl t ck baa ca pre charge 2 t ck valid when a burst read command is issued to a ddr sdram, a prechcrge co mmand may be issued to the same bank before the read burst is complete. the following functionality determines when a precharge command may be given during a read burst and when a new bank activate command may be issued to the same bank. 1. for the earliest possible precharge command without interrupt ing a read burst, the precharge command may be given on the ris ing clock edge which is cl clock cycles before th e end of the read burst where cl is the ca s latency. a new bank activate command may be issued to the same bank after trp. 2. when a precharge command interrupts a read burst operation, the precharge command may be given on the rising clock edge whic h is cl clock cycles before the last data from the interrupted read burst where cl is the cas latency. once the last data word has been output, the output buffers are tristated. a new bank activa te command may be issued to the same bank after trp. disable auto precharge all bank baa
40 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary read interrupted by a write & burst stop (@ bl=8, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high read qa0 qa1 t ch t cl t ck baa bab burst stop ca cb write db0 db1 db2 db3 db4 db5 db6 db7 disable auto precharge disable auto precharge
41 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary read interrupted by read (@ bl=8, cl=2) 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command high read qa0 qa1 qb0 qb1 qb2 qb3 qb4 qb5 t ch t cl t ck baa bab ca cb qb6 qb7 read t ccd disable auto precharge
42 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary dm function (@bl=8) only for write 0 1 2 3 4 5 6 7 8 9 10 high write baa ca da0 da1 da2 da3 da4 da5 da6 da7 t ch t cl t ck disable auto precharge ck ckb cke csb rasb casb ba0,ba1 a10/ap addr web dqs dq dm command
43 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary power up & initialization sequence ck ckb cke vdd dqs dq dm lvcmos high level vddq command a0-a9, a11 nop pre ar ar mrs emrs act nop 3 nop code code ra a10 code code ra ba0, ba1 ba0=l ba ba1=l ba0=h ba1=l high-z high-z t ch t cl t ck t is t ih t is t ih t is t ih t is t ih t=200us power-up: v dd and ck stable t rp 4 t rfc 4 t rfc 4 t mrd 4 extended mode register load mode register notes: 1. pre = precharge command, mrs = load mode register command, ar = auto refresh command act = active command, ra = row address, ba = bank address 2. nop or deselect commands are required for at least 200us. ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ ~ t mrd 4 3. other valid commands are possible. 4. nops or deselects are required during this time. nop 2
44 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary mode register set 0 1 2 3 4 5 6 7 8 9 10 ck ckb cke csb rasb casb web ba0, ba1 a10/ap addr dm dq dqs high t ch t cl t ck 2 clock min. high-z high-z high-z t rp precharge command all bank mode register set command any command note 1 power & clock must be stable for 200us before precharge all banks
45 EMD56324P 256m: 8m x 32 mobile ddr sdram rev 0.0 preliminary em x xx xx x x x - xx x x x 1. emlsi memory 2. device type 3. density 5. bank 6. interface ( vdd,vddq ) 8. package 9. speed 1. memory component 2. device type 8 ------------------------ low power sdram 9 ------------------------ sdram d ------------------------ mobile ddr 3. density 32 ----------------------- 32m 64 ----------------------- 64m 28 ----------------------- 128m 56 ----------------------- 256m 12 ----------------------- 512m 1g ----------------------- 1g 4. organization 04 ---------------------- x4 bit 08 ---------------------- x8 bit 16 ---------------------- x16 bit 32 ---------------------- x32 bit 5. bank 2 ----------------------- 2 bank 4 ----------------------- 4 bank 6. interface ( vdd,vddq ) v ------------------------- lvttl ( 3.3v,3.3v ) h------------------------- lvttl ( 3.3v,2.5v ) k ------------------------- lvttl ( 3.0v,3.0v ) x ------------------------- lvttl ( 3.0v,2.5v ) u ------------------------- p-lvttl ( 3.0v,1.8v ) s ------------------------- lvcmos ( 2.5v,2.5v ) r ------------------------- lvcmos ( 2.5v,1.8v ) p ------------------------- lvcmos ( 1.8v,1.8v ) 7. version blank ----------------- 1st generation a ------------------------2nd generation b ----------------------- 3rd generation c ----------------------- 4th generation d ----------------------- 5th generation 8. package blank ----------------- kgd u ------------------------44 tsop2 p ----------------------- 48 fpbga z ----------------------- 52 fpbga y ----------------------- 54 fpbga v ----------------------- 90 fpbga 9. speed 60 ---------------------- 6.0ns (166mhz cl=3) 70 ---------------------- 7.0ns (143mhz cl=3) 75 ---------------------- 7.5ns (133mhz cl=3) 7c ---------------------- 7.5ns (133mhz cl=2) 80 ---------------------- 8.0ns (125mhz cl=3) 8c ---------------------- 8.0ns (125mhz cl=2) 90 ---------------------- 9.0ns (111mhz cl=3) 10 ---------------------- 10.0ns (100mhz cl=3) 1c ---------------------- 10.0ns (100mhz cl=2) 12 ---------------------- 12.0ns (83mhz cl=2) 1l ---------------------- 25.0ns (40mhz cl=1) 10. power u ---------------------- low low power l ---------------------- low power s ---------------------- standard power 11. temperature c ---------------------- commer cial ( 0?c ~ 70?c ) e ---------------------- extended (-25?c ~ 85?c ) i ---------------------- industrial (-40?c ~ 85?c ) 4. organization 10. power sdram function guide 7. version 11. temperature

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